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(1 - 6 of 6)

Title: High performance IC clock networks with grid and tree topologies
Author(s): Lu, Jianchao
Advisor(s): Taskin, Baris
Date: 2011-05
Type: Thesis

Title: Network-on-Chip (NoC) Architectures for Exa-scale Chip-Multi-Processors (CMPs)
Author(s): More, Ankit
Advisor(s): Taskin, Baris
Date: 2013-06
Type: Thesis

Title: Delay insertion method in clock skew scheduling
Author(s): Taskin, Baris
Date: 2006-04
Type: Article

Title: Design-for-debug, A vital aspect in education
Author(s): Nagvajara, Prawat, 1958-, Taskin, Baris
Date: 2007-04-15
Type: Presentation

Title: Timing-driven physical design for VLSI circuits using resonant rotary clocking
Author(s): Taskin, Baris, Wood, John, Kourtev, Ivan S.
Date: 2006-08-06
Type: Presentation

Title: A timing optimization method based on clock skew scheduling and partitioning in a parallel computing environment
Author(s): Taskin, Baris, Kourtev, Ivan S.
Date: 2006
Type: Presentation