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Optimal reconfigurable HW/SW co-design of load flow and optimal power flow computation
Please use this identifier to cite or link to this item:
http://hdl.handle.net/1860/2556
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| Title: | Optimal reconfigurable HW/SW co-design of load flow and optimal power flow computation |
| Authors: | Murach, M.
Vachranukunkiet, Petya
Nagvajara, Prawat
Johnson, Jeremy
Nwankpa, Chikaodinaka Okechi Dike |
| Keywords: | FPGA
Optimal Power Flow
Sparse
LU
Linear Programming
Load Flow |
| Issue Date: | 18-Jun-2006 |
| Publisher: | Institute of Electrical and Electronics Engineers (IEEE) |
| Citation: | Paper presented at IEEE Power Engineering Society General Meeting, Montreal, Quebec, Canada. |
| Abstract: | Load flow and Optimal Power Flow (OPF)
constitute core computations used in energy market
operation. We considered different design partitions of
computational tasks for a desktop computer equipped with
Field Programmable Gate Array (FPGA). Load flow and
OPF require Lower-Upper triangular matrix
decomposition (LU). The number of clock cycles required
for data transfer and floating-point operations were used
as performance measures in determining optimal
hardware/software partitions for each problem. Optimal
partition performance is achieved by assigning the Lower-
Upper triangular decomposition (LU) and matrix
multiplication operations to custom hardware cores. A
comparison between the proposed partition and software
implemented using a state-of-the-art sparse matrix
package running on a 3.2 GHz Pentium 4 shows a six-fold
speedup. |
| URI: | http://dx.doi.org/10.1109/PES.2006.1709358
http://hdl.handle.net/1860/2556 |
| Appears in Collections: | Faculty Research and Publications (ECE)
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